# 留学生作业代写 EEEN2003J Digital Electronics – cscodehelp代写

Beijing Dublin International College EEEN2003J Digital Electronics
Equipment: Pen and paper! PC with “logisim” installed Submission
Introduction
The purpose of this laboratory is to further gain experience designing combinatorial logic circuits. You will firstly design a 1 bit half adder and then, using this half adder as a building block, create a 1 bit full adder. Then 4 of these full adders will be combined together to create a 4 bit ripple adder in Logisim.
In the second part of this Lab, you will again use Logisim to investigate how feedback in a digital circuit makes the circuit implicitly time-dependent. You will observe the inner workings of various latches, and you will experiment with the all-important Edge-triggered D-flipflop.
You are required to design and test this circuit.
Tip: Logisim support the concept of having several circuits within the one project file. Doing this allows you to re-use circuits in more complicated designs. Reusing one circuit design multiple times in a larger more complicated circuit. You can create these from the menu item Project->Add Circuit:
If you correctly label the inputs and outputs from each circuit, they can be re-used (several times with one design) as “sub-circuits” in a larger circuits, e.g. the half adder can be used to create a full adder which in turn can be used to create a multi-bit ripple adder. You can also use this technique to create latches which in turn can be modified to become flip-flops.
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A 1-bit half adder has two 1-bit inputs, X and Y, and two outputs, Sum (S) and a Carry (C) bit , the truth table is:
00 00 01 01 10 01 11 10
You need to design a circuit to implement the above truth table.
You should implement this in logisim, and test it for all possible input combinations.
A 1-bit full adder is similar to a half adder but it allows also a Carry in bit (Cin), the truth table is as follows:
000 011 101 110 001 010 100 111
This can be designed using the Karnaugh map technique leading to an efficient two level logic implementation, however it can be implemented more efficiently (i.e. using less gates) using multi-level logic. In particular the following circuit, built from two half adders, is very efficient:
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You should implement a 1-bit full adder, using either the karnaugh map technique, or, by using the above circuit – either will work!
Verify the operation of you circuit for all possible combinations of inputs.