Department of Electronic Engineering
ELE00067M Digital Design Coursework Assessment 2021/22 SUMMARY DETAILS
This coursework (Final Project) contributes 40% of the assessment for this module.
Clearly indicate your Exam Number on every separate piece of work submitted.
Submission is via the VLE submission point. The deadline is 12:00 noon on 24 January 2022, Spring Term, Week 3, Monday. Please try and submit early as any late submissions will be penalised. Assessment information including on late penalties is given in the Statement of Assessment.
It is your responsibility to ensure that you understand and comply with the University’s policy on academic integrity. If this is your first year of study at the University then you also need to complete the mandatory Academic Integrity Tutorial. Further information is available at http://www.york.ac.uk/integrity/.
In particular please note:
Unless the coursework specifies a group submission, you should assume that all submissions are individual and should therefore be your own work.
All assessment submissions are subject to the Department’s policy on plagiarism and,
wherever possible, will be checked by the Department using Turnitin software.
ELE00067M Digital Design
Final project: Part III
Design of a (parameterizable) single-cycle datapath
THE PROJECT SHOULD BE DONE INDIVIDUALLY
There is no formal report structure – you will be marked on the items listed within the script. The report will include code printout and simulation screenshots – see Lab 1 Appendices for guidelines.
Each part of the script must be handed in as a separate pdf file within a .zip archive, via the VLE by the deadline indicated on the front page of the script. In other words, 5 pdf files should be submitted in a single archive.
Your exam number should be printed on the first page of each pdf file.
The PDF files should be named Yxxxxxxx_DDMSc_PjP#.pdf, where the Yxxxxxxx is your exam number and the # is the part number (1 to 5).
In all cases, read carefully the instructions on the VLE submission page. Failure to follow the instructions could lead to your assignment not being marked and in any case to a mark penalty.
Submission weight on module mark: 40% Mark breakdown [100 marks]:
General issues (e.g. documentation, layout and comments, structural issues): 20 marks
Part 1 (e.g. VHDL code, testbench, simulation): 15 marks
Part 2 (e.g. VHDL code, testbench, simulation): 15 marks
Part 3 (e.g. VHDL code, testbench, simulation): 10 marks
Part 4 (e.g. VHDL code, testbench, simulation): 20 marks
Part 5 (e.g. VHDL code, testbench, simulation): 20 marks
Note 1: All scripts assume that you have access to version 2017.4 of the Vivado toolchain, available in the Departmental computer rooms. If you will be working remotely, instructions on how to install the free version on your own PC are available on the module website.
Note 2: You are absolutely free to exchange ideas and discuss the assessments with your fellow students. However, any instance of sharing code will be considered plagiarism and hence academic misconduct. As a “quick” rule, you can talk as much as you want (short of reading out the code you wrote), but you should never show your work to anyone else and much less exchange files. If you have any doubts as to what is allowed, do not hesitate to contact me.
A parameterizable datapath
The objective of this task is to design the datapath for a single-cycle processor implementation: The datapath should use the ALU and the register bank implemented in the previous two labs.
The connections between components (including muxes) should correspond to the architecture described in the lectures with the label “Architecture B” (attached at the end of this script as a reminder). Ignore the control logic for the moment – all control signals, immediate values, addresses, and flags should be I/O ports of your entity and assigned/read in the testbench.
The size of the data in the datapath should be parameterizable and defined by a generic value. Again, you can use the size and log2 functions.
The operation of the datapath should be partially verified (the full verification will only occur at the end of the project) with the following sequence of instructions (for which you will have to define the necessary control signals and immediate values, provide them at the appropriate time, and verify that all outputs are correct and that timing is respected). For the testbench, assume a data and address width of 16 and 32 registers in the register bank. All don’t care values should be assigned value ‘0’ in the testbench.
inc R1, R0;
addi R2, R0, 0005;
shl R3, R1, 3;
storr R2, R3;
loadi R5, 1f1f;
[store the value 1 into register R1]
[store value 5 into register R2]
[store value 8 into register R3]
[store 5 into memory at address 8]
[load into R5 the contents of the memory at address 1F1F – assume
that the value in question is 7 and provide it in your testbench]
Note: the DATA memory should not be implemented, but emulated in the testbench (providing the data value for the load operations at the correct time). Also, the OEN signal should be generated by the testbench, but should not be used by the datapath (eventually, it will be sent directly to the data memory together with the data to be written).
The report for this exercise should include:
The commented VHDL code for the datapath and its components. Note: screenshots are NOT
The commented VHDL testbench. Use a record to define the control signals. Note: screenshots
are NOT accepted.
A printout of the simulator results for the testbench – please comment the screenshots to
highlight the operations being performed and make sure that the result of each operation
(content of the written register or output to memory) is clearly readable.
The “RTL Component Statistics” and “RTL Hierarchical Component Statistics” parts of the
Screenshots of the schematics generated by the RTL analysis for the top level only.