# 程序代写代做代考 PowerPoint 演示文稿

PowerPoint 演示文稿

CO101
Principle of Computer

Organization
Lecture 09: Single Cycle

Processor 2

Liang Yanyan

Macau of University of Science and Technology

Recap: A Single Cycle Datapath
• We have everything except control signals, this lecture will show you how to

generate the control signals.

2

Instr[31-0]

Instruction
Memory

PC

4

Write Data

Register

File

Data 1

Data 2

ALU

zero

RegWrite

Data
Memory

Write Data

MemWrite

Sign
Extend 16 32

MemtoReg

ALUsrc

Shift
left 2

PCsrc

RegDst

1

1

1

0
0

0

0

1

Instr[15-0]

Instr[25-21]

Instr[20-16]

Instr[15-11]

Shift
left 2

0

1
32

Instr[25-0]

26
PC+4[31-28]

28

Jump

ALUctr

SignExt

The Big Picture: Where are We Now?
• The Five Classic Components of a Computer

• Today’s Topic: Designing the Control for the Single Cycle

Datapath

3

Control

Datapath

Memory

Processor
Input

Output

Step 4: Designing control signals
• Control signals are used to control the datapath to

perform necessary operations.
• Need to decide what control signals are required such

that we can fully control our processor to perform
calculation.

• Example: add t0, t1, t2
• Need the ALU to perform addition.
• As a result, we need a control signal “ALUctr” to control the ALU

to perform necessary operation.

4

• Selecting the operations to perform (ALU, Register File

• Controlling the flow of data (multiplexor inputs)
• Information comes from the 32 bits of the instruction

5

 Observations
 op field always in bits 31-26
 addr of two registers to be read are always specified by the rs and rt

fields (bits 25-21 and 20-16)
 base register for lw and sw always in rs (bits 25-21)
 addr. of register to be written is in one of two places – in rt(bits 20-

16) for lw; in rd (bits 15-11) for R-type instructions
 offset for beq, lw, and sw always in bits 15-0

(Almost) Complete Single Cycle Datapath

6

Meaning of the Control Signals
• RegDst: Register destination. 0 → rt, 1 → rd.
• RegWrite: Write register file or not. 0 → no, 1 → yes.
• ALUctr: Operation of ALU, “add”, “sub”, “or”, etc.
• ALUsrc: Select data for ALU. 0 → Register file, 1 →

Immediate.
• MemWrite: Write data memory or not. 0 → no, 1 → yes.
• MemRead: Read data memory or not. 0 → no, 1 → yes.
• MemtoReg: Select data for writing register file. 0 → ALU,

1 → data memory.
• PCsrc: Branch or not. 0 → no, 1 → yes.
• Jump: Jump or not. 0 → no, 1 → yes.
• SignExt: Perform sign or zero extend. “sign” or “zero”.

7

Steps in add instruction

• add rd, rs, rt

• mem[PC] Fetch the instruction

from memory

<21:25>

<16:20>

<11:15>

<0:15>

imm16 Rd Rs Rt

PCsrc

Inst
Memory

DATA PATH

Control logic

Op

<21:25>

Fun

RegWr

Datapath after adding control logic: Control,
ALU control, and

17

Why do we need two steps
(Control and ALU control) to
generate control signals for
the ALU?

ALU Control
• Controlling the ALU uses of multiple decoding levels

• main control unit generates the ALUOp bits
• ALU control unit generates ALUcontrol bits

18

ALU Control Truth Table
• ALU’s operation based on instruction type and function

code.

19

ALU Control Logic
• From the truth table can design the ALU Control logic

20

Complete Datapath with Control Unit

21

R-type Instruction Data/Control Flow

22

Load Word Instruction Data/Control Flow

23

Store Word Instruction Data/Control Flow

24

Branch Instruction Data/Control Flow

25

Main Control Unit

26

Control Unit Logic
• From the truth table can design the Main Control logic

27

Review: Handling Jump Operations
• Jump operation have to

• replace the lower 28 bits of the PC with the lower 26 bits of the
fetched instruction shifted left by 2 bits

28

Adding the Jump Operation

29

Main Control Unit of j

30

Single Cycle Implementation Cycle Time
• Single Cycle Implementation Cycle Time approach is not

used because it is very slow.
• Clock cycle must have the same length for every

instruction.

• What is the longest path (slowest instruction)?

31

Instruction Critical Paths
• Calculate cycle time assuming negligible delays (for

muxes, control unit, sign extend, PC access, shift left 2,
wires) except:
• Instruction and Data Memory (4 ns)
• ALU and adders (2 ns)
• Register File access (reads or writes) (1 ns)

32

• Uses the clock cycle inefficiently – the clock cycle must

be timed to accommodate the slowest instruction.
• especially problematic for more complex instructions like floating

point multiply.

• May be wasteful of area since some functional units (e.g.,
adders) must be duplicated since they can not be shared
during a clock cycle.

• But it is simple and easy to understand.

33

Summary
• Single cycle datapath => CPI=1

• Long cycle time
• Cycle time for load is much longer than needed for all other

instructions
• 5 steps to design a processor

• 1. Analyze instruction set => datapath requirements
• 2. Select set of datapath components
• 3. Assemble datapath meeting the requirements
• 4. Analyze implementation of each instruction to determine

setting of control signals
• 5. Assemble the control logic

• Usually control is the hard part
• Complex control => long cycle time

34

CO101�Principle of Computer Organization
Recap: A Single Cycle Datapath
The Big Picture: Where are We Now?
Step 4: Designing control signals
(Almost) Complete Single Cycle Datapath
Meaning of the Control Signals
Steps in add instruction
The Single Cycle Datapath during add
The Single Cycle Datapath during sub??
The Single Cycle Datapath during addi
The Single Cycle Datapath during Load
The Single Cycle Datapath during Store??
The Single Cycle Datapath during Store
The Single Cycle Datapath during Branch
Step 5: Adding control logic
Datapath after adding control logic: Control, ALU control, and
ALU Control
ALU Control Truth Table
ALU Control Logic
Complete Datapath with Control Unit
R-type Instruction Data/Control Flow
Load Word Instruction Data/Control Flow
Store Word Instruction Data/Control Flow
Branch Instruction Data/Control Flow
Main Control Unit
Control Unit Logic
Review: Handling Jump Operations
Adding the Jump Operation
Main Control Unit of j
Single Cycle Implementation Cycle Time
Instruction Critical Paths