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Integrated Electronics & Design
nMOS logic IC design
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⚫ NMOSlogic(examples) ⚫ Calculation
⚫ DesignExercise
Transistor in Linear Mode VD
Assuming V
n+ – V(x) +
VGS-VT VDS
T : ID = b0 W/L [(VGS – VT)VDS – VDS2/2]
b0 = nCox
R = VDS / ID
Transistor in Saturation Mode
Assuming V
VDS > VGS – VT
n+ – VGS – VT + n+ Pinch-off
: ID = (b0/2) W/L [(VGS – VT) 2]
NMOS Logic (Inverter): Example 1
Calculate W/L with the following specification: -4 -2
1) RL=5k. 2) b= b0(W/L), and b0= 1.8*10 AV . 3) VT =0.3V. 4) VDD=5V.
The aspect ratio, W/L, is ??
Layout(版图)
NMOS Logic (Inverter): Example 1
Calculate W/L with the following specification: 1) RL=5k. 2) b= b0(W/L), and b0= 1.8*10-4AV-2. 3) VT =0.3V. 4) VDD=5V.
If Vin = VDD, let VOut = 0.1V << VT Potential divider:
RD/(RD+RL)=VOut/VDD=0.1/5=0.02
→ RD ≈ 100
ID= b[(VG-VT)VD-VD2/2] b[(VG-VT)VD]
RD= VOut/ID ={b[(VDD-VT)]}-1 =1/[b(5-0.3)]=100
→ b ≈ 20*10-4. Therefore, the aspect ratio, W/L, is 12.
NMOS Logic (Inverter): Example 1
Calculate W/L with the following specification: 1) RL=5k. 2) b= b0(W/L), and b0= 1.8*10-4AV-2. 3) VT =0.3V. 4) VDD=5V.
NMOS Logic (Inverter): Example 1
Calculate W/L with the following specification: 1) RL=5k. 2) b= b0(W/L), and b0= 1.8*10-4AV-2. 3) VT =0.3V. 4) VDD=5V.
NMOS Logic (Inverter): Example 2
Calculate W/L of Load with the following specification:
1) The aspect ratios of D is 12.
2) b= b0(W/L), and b0= 1.8*10-4AV-2. 3) VT = 0.3V. 4) VDD=5V.
=24 L =2
NMOS Logic (Inverter): Example 2
Calculate W/L of Load with the following specification:
1) The aspect ratios of D is 12.
2) b= b0(W/L), and b0= 1.8*10-4AV-2. 3) VT = 0.3V. 4) VDD=5V.
If Vin = VDD, let VOut = 0.1V:
ID = bD[(Vin-VT)VOut-VOut2/2] RD= VOut/ID =(12b0[(VDD-VT)])-1 =100
[RD/(RD+RL)]=VOut/VDD=0.1/5=0.02
ID =bL(VDD -VT)2/2
R = (V -V )/I = 4.9*2/[b (5-0.3)2] =5k LDDoutD L
→ bL = 8.9*10-5 → aspect ratio of load = 0.5
NMOS Logic (Inverter): Example 2
Calculate W/L of Load with the following specification:
1) The aspect ratios of D is 12.
2) b= b0(W/L), and b0= 1.8*10-4AV-2.
3) VT = 0.3V. 4) VDD=5V.
W/L of Load= 0.5
NMOS Logic (Inverter): Example 2
Calculate W/L of Load with the following specification:
1) The aspect ratios of D is 12.
2) b= b0(W/L), and b0= 1.8*10-4AV-2.
3) VT = 0.3V. 4) VDD=5V.
NMOS Logic (NOR): Example 3
Calculate W/L of Load with the following specification:
1) The aspect ratios of D is 12.
2) b= b0(W/L), and b0= 1.8*10-4AV-2.
3) VT = 0.3V. 4) VDD=5V. R Solution: L let VOut = 0.1V:
ID = bD[(VinA-VT)VOut-VOut2/2] RD= VOut/ID =(bD[(VDD-VT)])-1 =100
[0.5RD/(0.5RD+RL)]=VOut/VDD=0.1/5=0.02
→ RL=2.5k
ID =bL(VDD -VT)2/2
R = (V -V )/I = 4.9*2/[b (5-0.3)2] =2.5k LDDoutD L
→ bL =1.8*10-4 → aspect ratio of Load= 1.
Example: Design Exercise 1
➢ ➢ ➢ ➢ ➢ ➢
It consists of an n channel NOR gate feeding an inverter.
The transistors A and B are the termed driver MOSFETs.
The process parameters are defined:
b0 = 1.8×10-4AV-2 VT = 0.3V VDD=5V
RS = 100/sq
W/L = 12/1
Example: Design Exercise 2 Layout design of the NMOS IC
➢ ➢ ➢ ➢ ➢ ➢
It consists of an n channel NOR gate feeding an inverter.
The transistors A and B are the termed driver MOSFETs.
The process parameters are defined:
b0 = 1.8×10-4AV-2 VT = 0.3V VDD=5V
RS = 100/sq
NMOS Logic (NOR): Example 4
Calculate W/L with the following specification: 1) RL=5k. 2) b= b0(W/L), and b0= 1.8*10-4AV-2. 3) VT =0.3V. 4) VDD=5V.
If VA=VB=VDD, let VOut = 0.1V << VT Potential divider:
0.5RD/(0.5RD+RL)=VOut/VDD=0.1/5=0.02
→ RD ≈ 200
ID= b[(VG-VT)VD-VD2/2] b[(VG-VT)VD]
RD=VOut/ID={b[(VDD-VT)]}-1 =1/[b(5-0.3)]=200
→ b ≈ 10*10-4. Therefore,
the aspect ratio, W/L, is
Example: Design Exercise 2
Layout design of the nMOS IC shown in Fig.1
➢ ➢ ➢ ➢ ➢ ➢
It consists of an n channel NOR gate feeding an inverter.
The transistors A and B are the termed driver MOSFETs.
The process parameters are defined:
b0 = 1.8×10-4AV-2 VT = 0.3V VDD=5V
RS = 100/sq
NMOS Logic (Inverter): Example 5
Calculate W/L of Load with the following specification:
1) The aspect ratios of D is 6.
2) b= b0(W/L), and b0= 1.8*10-4AV-2. 3) VT = 0.3V. 4) VDD=5V.
If Vin = VDD, let VOut = 0.1V:
ID = bD[(Vin-VT)VOut-VOut2/2] RD= VOut/ID =(6b0[(VDD-VT)])-1 =200
[RD/(RD+RL)]=VOut/VDD=0.1/5=0.02
→ RL ≈ 10k
ID =bL(VDD -VT)2/2
R = (V -V )/I = 4.9*2/[b (5-0.3)2] =10k LDDoutD L
→ bL = 4.4*10-5 → aspect ratio of load = 0.25
Example: Design Exercise 2
Layout design of the nMOS IC shown in Fig.1
➢ ➢ ➢ ➢ ➢ ➢
It consists of an n channel NOR gate feeding an inverter.
The transistors A and B are the termed driver MOSFETs.
The process parameters are defined:
b0 = 1.8×10-4AV-2 VT = 0.3V VDD=5V
RS = 100/sq
W=4, L=16
⚫ NMOSlogic(examples) ⚫ Calculation
⚫ DesignExercise
NMOS Logic (Inverter): Example 1 5K
NMOS Logic (Inverter): Example 1 5K
For small LR/WR: (e.g. LR/WR=9)
For large LR/WR: (e.g. LR/WR=20)
Squares are used to calculate the length, L. 22
NMOS Logic (Inverter): Example 1
For small LR/WR: (e.g. LR/WR=9)
For large LR/WR: (e.g. LR/WR=20)
Every square must disappear when drawing your layout
NMOS Logic (Inverter): Example 1 5K
NMOS Logic (Inverter): Example 1 5K
Active mask for n+ region
NMOS Logic (Inverter): Example 1 RL=5k & Rs=100/sq
RL=Rs(LR/WR) → LR/WR=50
NMOS Logic (Inverter): Example 2 W/L
VDD Aluminium
Load device via to VDD
Polysilicon gate of load MOSFET with a via to Aluminium and VDD
Drain of driver with a via to output
Source Via to load MOSFET
polysilicon gate as input to circuit
Source of driver with a via
Ground line (Aluminium)
NMOS Logic (Inverter): Example 2 Mask1
NMOS Logic (Inverter): Example 2 Mask2
NMOS Logic (Inverter): Example 2 Mask3
NMOS Logic (Inverter): Example 2 Mask4
NMOS Logic (Inverter): Example 2
VDD Aluminium
Load device via to VDD
Drain of driver with a via to output
polysilicon gate as input to circuit
Source of driver with a via
Ground line (Aluminium)
Polysilicon gate of load MOSFET with a via to Aluminium and VDD
Source Via to load MOSFET
NMOS Logic (NOR): Example 3
⚫ NMOSlogic(examples) ⚫ Calculation
⚫ DesignExercise
Example: Design Exercise 2
Layout design of the nMOS IC shown in Fig.1
➢ ➢ ➢ ➢ ➢ ➢
It consists of an n channel NOR gate feeding an inverter.
The transistors A and B are the termed driver MOSFETs.
The process parameters are defined:
b0 = 1.8×10-4AV-2 VT = 0.3V VDD=5V
RS = 100/sq
Example: Design Exercise 2
⚫ Design rules:
⚫ The driver transistors should have channel length L equal to the minimum feature size m. The width of the drivers W, which must always be a whole number (n) of minimum feature sizes (nm), and the overall value of W must be chosen to give the required output voltage. This must be significantly less than the threshold voltage of the third gate C if this transistor is to stay off.
⚫ The layouts must take account of the alignment accuracy a.
W/L=6 W/L=6
Example: Design Exercise 2
1) The Design involves producing the patterns corresponding
to each of the stages of the process already discussed.
2) Each of the patterns should be drawn on graph paper with
a stipulated scale. (e.g 1m per cm.)
3) The patterns would be transferred at a later stage to glass
masks, as opaque regions. There are 4 masks :
M1. define the device area (active) M2. define the gate stripe (poly) M3. define the contacts (contact) M4. define the metal pattern (metal)
Example: Design Exercise 1
It consists of an n channel NOR gate feeding an inverter.
The transistors A and B are the termed driver MOSFETs.
The process parameters are defined:
b0 = 1.8×10-4AV-2 VT = 0.3V VDD=5V
RS = 100/sq
HINTS: Liverpool notes.
➢ ➢ ➢ ➢ ➢ ➢
W/L = 12/1
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