CS代考计算机代写 Sequential Circuits

Sequential Circuits

COMP273 McGill
á RS Latch
á D Latch
á D Flip flop á T Flip flop

COMP273 McGill
Sequential Circuits á Combinatorialcircuitshavenomemory
± Output is simply a function of inputs
á Sequentialcircuits}vö]v^êöö_
± Combinatorial circuits + memory
± The mechanism for remembering information (i.e., bits) inside the CPU and in the main memory.
± How to remember things?
á Write it down
á Repeat it to yourself (sequential circuits style)


COMP273 McGill
á TwoinputsSandR
± S = 1, set output to 1 ±R=1,resetoutput to0
± S, R are both 0, hold the values
2Z ^2 Y2 Yñ2 Ï2 Ï2 Q Q’ Ï2Ì21 0 Ì2Ï20 1
RS Latch

COMP273 McGill
RS Latch ± When S, R are both 1, invalid
á Problem:
2Z ^2 Y2 Yñ2
Ï2 Ï2 Q Q’ Ï2Ì21 0 Ì2Ï20 1
Ì2 Ì2 invalid invalid

á Mechanismforsynchronizinginputsandoutputs. á Metronome
á Clock speed is in Gigahertz
COMP273 McGill https://bestanimations.com/gifs/Black-And-White-Old-Metronome.html 31

á Recall that it takes time for combinatorial circuits to produce results.
á Wantresultsto
be finished before we store the result somewhere
COMP273 McGill
± e.g., carry ripple in adder
http://goo.gl /n3fKv

á WhenC=0,holdvaluesofQandQ’
á WhenC=1,D=1,thensetQ=1,Q’=0
á WhenC=1,D=0,thenresetQ=0,Q’=1 á Impossible for R and S to be both 1
D Latch
COMP273 McGill 34

á Still not good enough
± Data passes freely though the circuit while C =1.
COMP273 McGill
± Mightwantdothingslikex:=x+27
D Latch
± What happens if we combine an array of D latches with a combinatorial adder circuit?


D flip-flop
á TwoDlatches.Oneforreadingandoneforwriting
á Mechanism prevents data from being read/write at the same time
á By putting an inverter, change when the falling edge is triggered
COMP273 McGill 37

COMP273 McGill
á WhenC=1
± write D into the first D latch ± Q does not change
á WhenC=0
D flip-flop
± Stop writing D into the first D-latch.
± The D value from the first D-latch is written into the second D-latch

COMP273 McGill
á á
D flip-flop Setup and Hold
Setup time: Input must be stable before the falling clock edge
Hold time: Input must also be stable after clock edge ± Hold times typically very small, or zero

Toggle Flip Flop
á ,}}lY[μâö}Uvo}l}uêtoggle
COMP273 McGill 40

á RS Latches á D Latch
á D Flip flop á T Flip flop
Review and more information
á Textbook: Appendix B.7 and B.8 of 5th and 6th edition á Nexttopic:Registers(usesequentialcircuits)
COMP273 McGill 41

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