CS代考 A Simple OS Structure – cscodehelp代写

A Simple OS Structure
Review of “Computer Organization”
Address Space
Operating Systems – CSCI 402
text (code)
data
dynamic (heap)
stack
x86 Processor
Bus
idx regs
EIP
ESP EBP …
seg regs CS
SS …
gen regs EAX EBX
…
other flags
…
32 A0-A31
32 D0-D31
RD WR LOCK INT
interrupt enabled
processor mode
Memory
Device Controller
1
321 0
Copyright ý . Simple OS Structure
Review of “Computer Organization”
Address Space
x86 Processor
Bus
Operating Systems – CSCI 402
text (code)
data
dynamic (heap)
stack
idx regs
EIP
ESP EBP …
seg regs CS
SS …
gen regs EAX EBX
…
other flags
…
32 A0-A31
32 D0-D31
RD WR LOCK INT
interrupt enabled
processor mode
Memory
Device Controller
2
321 0
Copyright ý . Simple OS Structure
Review of “Computer Organization”
Address Space
Operating Systems – CSCI 402
text (code)
data
dynamic (heap)
stack
x86 Processor
Bus
idx regs
EIP
ESP EBP …
seg regs CS
SS …
gen regs EAX EBX
…
other flags
…
32 A0-A31
32 D0-D31
RD WR LOCK INT
interrupt enabled
processor mode
Memory
Device Controller
3
321 0
Copyright ý . Simple OS Structure
Review of “Computer Organization”
Address Space
Operating Systems – CSCI 402
text (code)
data
dynamic (heap)
stack
x86 Processor
Bus
idx regs
EIP
ESP EBP …
seg regs CS
SS …
gen regs EAX EBX
…
other flags
…
32 A0-A31
32 D0-D31
RD WR LOCK INT
interrupt enabled
processor mode
Memory
Device Controller
4
321 0
Copyright ý . Simple OS Structure
Review of “Computer Organization”
Address Space
idx regs
EIP
ESP EBP …
seg regs CS
SS …
gen regs
EAX EBX …
other flags
…
32 A0-A31
32 D0-D31
RD WR LOCK INT
Bus
Operating Systems – CSCI 402
text (code)
data
dynamic (heap)
stack
z=x+y
x86 Processor
mov &x ¡ú eax mov &y ¡ú ebx add(eax,ebx) mov eax ¡ú &z
interrupt enabled
processor mode
Memory
Device Controller
5
321 0
Copyright ý . Simple OS Structure
Review of “Computer Organization”
Address Space
Operating Systems – CSCI 402
text (code)
data
dynamic (heap)
stack
x86 Processor
Bus
idx regs
EIP
ESP EBP …
seg regs CS
SS …
gen regs EAX EBX
…
other flags
…
32 A0-A31
32 D0-D31
RD WR LOCK INT
interrupt enabled
processor mode
Memory
Device Controller
6
321 0
Copyright ý . Cheng

x86 Processor
Bus
Operating Systems – CSCI 402
Some important terms:
interrupt pending interrupt delivery
interrupt context thread context
A Simple OS Structure
idx regs
EIP
ESP EBP …
seg regs CS
SS …
gen regs EAX EBX
…
other flags
…
32 A0-A31
32 D0-D31
RD WR LOCK INT
interrupt enabled
processor mode
Memory
Device Controller
7
321 0
Copyright ý .
Traps are the general means for invoking the kernel from user code
Appl.
OS
HW
although we usually think of traps as errors
divide by zero, segmentation fault, bus error, etc.
but they don¡¯t have to be
system calls, page fault, etc.
Traps always elicit some sort of response
for programming errors, the default action is to terminate the user program
for system calls, the OS is asked to perform some service for page faults, the OS need to fix the virtual memory map
Operating Systems – CSCI 402
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Copyright ý . system calls through which user code can access the kernel in a controlled manner
any necessary checking on whether the request should be permitted can be done in the system call
all done in user mode
if all goes well
sets things up
traps into the kernel by executing a special machine instruction, i.e., the “trap” machine instruction
the kernel figures out why it was invoked and handles the trap
more in Ch 3
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Operating Systems – CSCI 402
A Special Kind Of Trap – System Calls
Invoking OS functionality in the kernel is more complex
but we want to make it look simple to applications must be done carefully and correctly
really cannot trust the application programmers to do the right thing every time
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Copyright ý .
An interrupt is a request from an external device for a response from the processor
most hardware interrupts are I/O completion interrupts
Appl. OS HW
Operating Systems – CSCI 402
an I/O device is telling the CPU, “I am done” (and “what do you want me to do next?”)
I/O devices are also hardware, they can run in parallel with the CPU, don¡¯t keep them idle unless you have nothing for them to work on
interrupts are handled independently of any user program unlike a trap, which is handled as part of the program that caused the trap where response to a trap directly affects that program
response to an interrupt may or may not indirectly affect the currently running program
often has no direct effect on the currently running
program
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Copyright ý .
An interrupt is an asynchronous event
it¡¯s asynchronous with respect to the executing entity (threads or OS)
Appl. OS HW
Operating Systems – CSCI 402
A trap occurs synchronously with respect to the executing entity when your thread executes a divide-by-zero instruction, we know exactly where it happens and we know when it will happen
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Copyright ý . Interrupt
There¡¯s also something called software interrupt generated programmatically (i.e., not by a device) when executing a machine instruction
Appl.
OS
HW
Operating Systems – CSCI 402
e.g., executing an “interrupt” machine instruction
x86 CPU uses a software interrupt (i.e., “int 0x2e”) to implement the “trap” machine instruction
other CPUs may have a separate “trap” machine instruction
this is very different from a hardware interrupt
although the mechanisms of handling interrupts are all very similar as we will see in Ch 3
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Copyright ý .
A program may establish a handler (i.e., a signal handler) to be invoked in response to the error
Appl.
OS
HW
Operating Systems – CSCI 402
the handler might clean up after the error and then terminate the program, or it might perform corrective action and continue with normal execution
more in Ch 2
The upcall mechanism
signals allow the kernel to invoke code that¡¯s part of user program
for example, you can set a timer to expire at a certain time, when it expires, the OS can use the upcall mechanism to call a specified user function on behalf of the user program
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Copyright ý . Systems – CSCI 402
1.3 A Simple OS
OS Structure
Processes, Address Spaces, & Threads
Managing Processes
Loading Program Into Processes Files
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Copyright ý . Cheng

recall that process is an abstraction of memory processor(s)
recall that thread is an abstraction of processor “execution context”
which represents the state of a process and its threads represents exactly “where you are” in the program
a thread needs some sort of a context to execute
Note: multiple meanings of the word “context” in this class
save (execution) context and restore (execution) context thread context vs. interrupt context
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Operating Systems – CSCI 402
Program Execution
Fundamental abstraction of program execution memory
address space
things that are addressable by the program are kept together here
in Sixth-Edition Unix, processes do not share address space
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Copyright ý . Cheng

current++;
for (j=0; prime[j]*prime[j] <= current; j++) { if (current % prime[j] == 0) goto NewCandidate; } prime[i] = current; } return(0); } Operating Systems - CSCI 402 A Program const int nprimes = 100; int prime[nprimes]; int main() { int i; int current = 2; prime[0] = current; for (i=1; i