代写代考 EIA-664) that specifies electrical characteristics of a particular variant – cscodehelp代写

Address Data Control
Monitor adapter
USB adapter
Data storage adapter

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Peripheral Bus, e.g. hdmi
Peripheral Bus, USB
Peripheral Bus, e.g. SATA
Registers ALU Control
Memory Bus, e.g. DDR4
Address Data Control
RAM (e.g. DDR4)
DIMM Memory
DIMM Memory
DIMM Memory
DIMM Memory
Local Bus, e.g. Peripheral Component Interconnect (PCI)

Computer buses
High speed bus (e.g. DDR4 memory bus or the ARM AHB) connects CPU to devices that require high data throughput, such as RAM. High speed buses are wide parallel buses (e.g. 128 bits wide) operating at very high clock frequencies ( 100-500 MHz).
Local bus (e.g. Peripheral Component Interconnect express PCIe or ARM APB) connects CPU to multiple adapters of peripheral devices. Modern local buses tend to be serial.
Peripheral buses, such as USB, HDMI, SATA are specified by consortia of peripheral device vendors. They specify electrical and logical interfaces for communicating with peripheral devices of a particular kind (displays, solid state drives, etc.). Modern peripheral buses tend to be serial.
Adapters (a.k.a controllers) are electronic circuits that provide the CPU with memory-mapped registers and additional circuitry to communicate/control the peripheral device(s) connected to the adapter via its peripheral bus

PC motherboard architecture
LPC bus = Low Pin Count bus (SPI)
By Original: Gribeco at French WikipediaDerivative work: Moxfyre at English Wikipedia – This file was derived from: Diagramme carte mère.png, CC BY-SA 3.0, https://commons.wikimedia.org/w/index.php?curid=3789066

ARM System-on-a-chip (SoC) architecture
ARM processor
Voltage regulator
System controller
Flash Programmer
Advanced Int. Ctrl.
Power Mgt. Ctrl.
Reset Ctrl.
Brownout Detect
Power On Reset
Prog. Int. Timer
Watchdog Timer
Real Time Timer
Debug Unit
Peripheral bridge
Peripheral data controller
Application-specific logic
Ethernet MAC
Two Wire Interface
USB device
Synchro Serial Ctrl
Timer/Counter 0-2
AHB = Advanced High-performance Bus APB = Advanced Peripheral Bus
EBI = External Bus Interface
By en:User:Cburnett – Own work in Inkscape based on en:Image:ARMSoCBlockDiagram.gif, CC BY-SA 3.0, https://commons.wikimedia.org/w/index.php?curid=2866881
ASB/ APB AHB
Memory controller

Computer Buses: Summary
Computer bus is a subsystem that connects computer components and transfers data between them.
Computer buses can be either parallel or serial. Modern computers use many different buses
High-speed parallel buses (e.g. DDR4 bus between CPU and RAM)
Local buses (e.g. PCIe bus between CPU and SATA Adapter)
Peripheral buses (e.g. SATA, USB, HDMI that connect computers to peripheral devices)
Adapter is a special component circuit that provides the CPU with memory mapped input/output registers to control particular peripheral bus and devices connected to it.

Interrupt driven input / output
Polled input / output keeps CPU busy, which is a waste of CPU time
Acceptable if CPU has nothing else to do (e.g. CPU in an embedded system)
Interrupt driven input / output solves this problem Interrupt is an unscheduled procedure call

Address Data Control
Interrupt ReQuest line (IRQ)
Interrupt ACKnowledge line (IACK)
Monitor adapter
USB adapter
Data storage adapter
Peripheral Bus, e.g. hdmi
Peripheral Bus, USB
Peripheral Bus, e.g. SATA
Registers ALU Control
Memory Bus, e.g. DDR4
Address Data Control
RAM (e.g. DDR4)
DIMM Memory
DIMM Memory
DIMM Memory
DIMM Memory
Local Bus, e.g. Peripheral Component Interconnect (PCI)

Interrupt driven input / output
Two hardware connections are added between the MIPS CPU and all IO adapters:
Interrupt Request (IRQ) Interrupt Acknowledge (IACK)
When a device needs attention, it asserts IRQ line (i.e. sets IRQ = “1”)
When the CPU detects IRQ equal to 1, it finishes executing the current instruction but instead of processing the next instruction, it:
1) Sets the bit corresponding to the device in the special Cause register
2) Saves the address of the next instruction in the special Exception Program Counter (ECP) register 3) Disables all interrupts by resetting the Interrupt Enable (IE) bit in the Status register
4) Jumps to the starting address of the Interrupt Service Routine (ISR)

Interrupt driven input / output (continued)
The Interrupt Service Routine:
1) Checks the Cause register to see which bit is set
2) Deals with that device, i.e. sends or receives information, via memory accesses 3) Sets IACK to 1
4) Enables all interrupts
5) Finally, jumps back to the address stored in EPC
At the same time, the IO adapter:
Waits until IACK is equal to 1 and then resets IRQ to 0

Direct Memory Access
Allows peripheral adapters to access (read from or write into) the main memory directly and independently of the CPU
Used for bulk data exchanges, such as reading or writing data blocks from/to data storage device, such as SSD, or to exchange data with a 3D graphics accelerator
A typical DMA interaction proceeds as follows:
1) CPU prepares the DMA transfer by writing the memory address and the number of bytes to transfer into special memory mapped DMA registers of the adapter.
2) CPU initiates the transfer by writing the appropriate command into the control register of the adapter 3) The adapter transfers the data by reading or writing consecutive memory words starting from the
specified address
4) Once the transfer is complete, the adapter causes an interrupt alerting the CPU that the transfer is

Differential Signalling

Low Voltage Differential Signalling (LVDS)
Technical standard (TIA/EIA-664) that specifies electrical characteristics of a particular variant of differential signalling
Used by SATA, FireWire, FPD-Link
Other high-speed interfaces use similar principle

Low Voltage Differential Signalling
Image source: https://commons.wikimedia.org/wiki/File:Basic_LVDS_circuit_operation.png Author: Dave at ti

Clocking information
LVDS does not have a separate CLK wire
Clock information is embedded into transmitted signal by either
inserting start-bit and stop-bit to guarantee bit transitions at regular intervals to mimic a clock signal1
encoding transmitted data using 8b/10b encoding
1https://en.wikipedia.org/wiki/Low-voltage_differential_signaling

LVDS vs other serial communication standards LVDS has lower
electromagnetic emissions due to coupling of wires
susceptibility to electromagnetic interference, which affects voltage, but not the direction of current.
impact on voltage and noise in the power supply lines Power consumption
LVDS requires
Carefully designed cables or PCB tracks
Special transmitter and receiver circuits, not ordinary logic gates

Digital systems are composed of standardised components, which requires standardisation of communication interfaces
Although serial communications require more complex hardware that parallel communications, they use less IC pins, which results in cheaper designs overall
Most High-speed interfaces, like SATA and PCIe are based on differential signalling

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