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OUR FIRST SEQUENTIAL LOGIC CIRCUIT: THE R-S LATCH
MCIT 593 – Introduction to Computer Systems Property of Penn Engineering 2

Basic Sequential Logic Circuit:

• R-S Latch
• Most fundamental unit for static memory
• Has the ability to “store” its last output
• called a “Latch” because it can “Latch” onto data coming in • “Cross-Coupled” NAND gates
• output of each NAND gate serves as input to the other • Two inputs: S (SET) & R (RESET)
• Two outputs: Q and NOT(Q) S
Notation: NOT(Q)= ~Q = Q’ = Q
Another common way
of drawing the same circuit
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• The R-S latch is a bi-stable circuit which means that it can happily exist in either of two stable states. Just like a see-saw.
• You can push the latch from one state to another by setting or resetting it with the S-R signals
• The logic levels are maintained because of the feedback paths from outputs to inputs.
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Analyzing Operation of a Latch
• First, recall truth table for a NAND gate:
• R-S Latch Operation:
• Best place to start is S=1, R=0
1st look at lower NAND gate
à Its inputs are: 0 and X (unknown)
Because Q is unknown at 1st
àProduces a 1 at its output (0) NAND (ANYTHING) = 1
MCIT 593 – Introduction to Computer Systems Property of Penn Engineering 5

Analyzing Operation of a Latch
• First, recall truth table for a NAND gate:
• R-S Latch Operation:
• Best place to start is S=1, R=0
Next, look at top NAND gate àIts inputs are: 1 and 1
Blue 1, comes from lower NAND àProduces a 0 at its output
Therefore, when S=1, R=0
The output of latch is: Q=0, ~Q=1
MCIT 593 – Introduction to Computer Systems Property of Penn Engineering 6

Analyzing Operation of a Latch
• First, recall truth table for a NAND gate:
• R-S Latch Operation: S=1
Truth Table for R-S Latch:
ACTION S R Q ~Q 00
RESET 1 0 0 1 11
Called the “RESET” action, as Q is set to 0 Also, notice: Q and ~Q opposite
MCIT 593 – Introduction to Computer Systems Property of Penn Engineering 7

Analyzing Operation of a Latch
• Truth table for a NAND gate:
ABC 001 011
• R-S Latch Operation:
• Next input case is called the “SET”, when inputs are: S=0, R=1
1st look at upper NAND gate
àIts inputs are: 0 and X (anything) àProduces a 1 at its output
Lower NAND gate
àInputs are: 1 and 1 àProduces a 0 at its output
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Analyzing Operation of a Latch
• Truth table for a NAND gate:
ABC 001 011
• R-S Latch Operation: S=0
Truth Table for R-S Latch:
ACTION S R Q ~Q 100
SET 0 1 1 0 RESET 1 0 0 1
SETs LATCH to have a “1” at the output
MCIT 593 – Introduction to Computer Systems Property of Penn Engineering 9

Analyzing Operation of a Latch
• Truth table for a NAND gate:
ABC 001 011
• R-S Latch Operation:
• Last valid input case is the “HOLD” S=1, R=1
• If we have just “SET” Latch, we will have Q=1, ~Q=0, already on outputs
Upper NAND gate
à Has S=1 & former value of ~Q=0 àProduces a 1 at its output
(same ~Q as when it started)
Lower NAND gate
àInputs are: 1 and 1
à Produces a 0 at its output (same Q)
MCIT 593 – Introduction to Computer Systems Property of Penn Engineering 10

Analyzing Operation of a Latch
• Truth table for a NAND gate:
ABC 001 011
• R-S Latch Operation:
Truth Table for R-S Latch:
ACTION S R Q ~Q S=1 1 00
Q SET0110 RESET 1 0 0 1 HOLD 1 1 1 0
HOLD’s value we “SET” last
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Analyzing Operation of a Latch
• Truth table for a NAND gate:
ABC 001 011
• R-S Latch Operation:
• Re-examine the “HOLD” S=1, R=1
• What if we had just “RESET” latch, outputs would already be: Q=0, ~Q=1, then:
Upper NAND gate
à Has S=1 & former value of ~Q=1 àProduces a 0 at its output
(same Q as when it started)
Lower NAND gate
àInputs are: 0 and 1
à Produces a 1 at its output (same ~Q)
MCIT 593 – Introduction to Computer Systems Property of Penn Engineering 12

Analyzing Operation of a Latch
• Truth table for a NAND gate:
• R-S Latch Operation: S=1
1 0 0 1 1 0
ABC 001 011
Truth Table for R-S Latch:
00 SET 0 1
HOLD 1 1 0 1
HOLD’s last value on its outputs!
OUTPUT depends on input and last output
MCIT 593 – Introduction to Computer Systems Property of Penn Engineering 13

Storage – Cross-Coupled NANDs (R-S Latch)
• Real circuits depend on both Q and ~Q
• Strange things may happen if both are 1
• What happens with S=0 and R=0? • Short answer: confusion
ACTION S R Q ~Q
ILLEGAL 0 0 1 1
SET 0 1 1 0 RESET 1 0 0 1 HOLD 1 1 1 0 HOLD 1 1 0 1
The next section of these slides shows how to prevent… …the R-S Latch from ever getting S=R=0 as its input
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A MORE ROBUST LATCH: THE GATED D-LATCH
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Gated D-Latch: Preventing “Illegal Action” of R-S Latch
Let’s add some logic to the R-S Latch…to prevent R-S’s illegal action
R-S Latch Truth Table
RESET 1 HOLD 1 HOLD 1 ILLEGAL 0
Protection Circuit’s Purpose
Careful examination of
the NAND gates helps us see that they prevent the RS latch from ever having 00 at its input
“Protection” Circuit
“Gated” D-Latch
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Gated D-Latch: Preventing “Illegal Action” of R-S Latch
Let’s add some logic to the R-S Latch…to prevent R-S’s illegal action
NAND Gate TT
A B NAND 0 0 1
0 1 1 101 110
R-S Latch Truth Table
RESET 1 HOLD 1 HOLD 1 ILLEGAL 0
Let’s examine our new Latch
D-Latch’s inputs:
WE = Write Enable
D-Latch outputs:
Q = DATA OUT
Q’ — not shown, but still there!
10 1 “Protection” Circuit
Let’s try inputs D=1, WE=1
“Gated” D-Latch
MCIT 593 – Introduction to Computer Systems Property of Penn Engineering 18

Gated D-Latch: Preventing “Illegal Action” of R-S Latch
Let’s add some logic to the R-S Latch…to prevent R-S’s illegal action
NAND Gate TT
R-S Latch Truth Table
D-Latch Truth Table
ACTION WE D Q
OPEN 1 1 1
OPEN 1 0 0 CLOSED 0 X 1 CLOSED 0 X 0
A B NAND ACTION S 001SET0 011 RESET1 101 HOLD1 110 HOLD1
10 ILLEGAL 0 0
We have our first “action”
When D=1 AND WE=1
It forces RS Latch to its SET action • Outputs Q=1 and Q’=0
We call this the “open” action
• We’ll see why this isn’t a SET for
the D-latch shortly
“Protection” Circuit
“Gated” D-Latch
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Gated D-Latch: Preventing “Illegal Action” of R-S Latch
Let’s add some logic to the R-S Latch…to prevent R-S’s illegal action
NAND Gate TT
A B NAND 0 0 1
0 1 1 101 110
R-S Latch Truth Table
D-Latch Truth Table
ACTION WE D Q
OPEN 1 1 1
OPEN 1 0 0 CLOSED 0 X1 1 CLOSED 0 X 0
Let’s change only WE = 0
• We keep D the same
• This forces the RS Latch to
HOLD the last output
RESET 1 HOLD 1 HOLD 1 ILLEGAL 0
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Gated D-Latch: Preventing “Illegal Action” of R-S Latch
Let’s add some logic to the R-S Latch…to prevent R-S’s illegal action
NAND Gate TT
A B NAND 0 0 1
0 1 1 101 110
R-S Latch Truth Table
D-Latch Truth Table
ACTION WE D Q
OPEN 1 1 1
OPEN 1 0 0 CLOSED 0 X1 1 CLOSED 0 X 0
Let’s change only WE = 0
RESET 1 HOLD 1 HOLD 1 ILLEGAL 0
• We keep D the same 01• This forces the RS Latch to
0 the last output is HELD
011 • WE stands for “Write Enable”
• When WE=0, the D-latch is “read-only”
• When WE=1, the latch is “writeable”
MCIT 593 – Introduction to Computer Systems Property of Penn Engineering 21
HOLD the last output
1 • Even if we change the “D” input,

Gated D-Latch: Preventing “Illegal Action” of R-S Latch
Let’s add some logic to the R-S Latch…to prevent R-S’s illegal action
NAND Gate TT
A B NAND 0 0 1
R-S Latch Truth Table
D-Latch Truth Table
ACTION WE D Q
OPEN 1 1 1
OPEN 1 0 0 CLOSED 0 X 1 CLOSED 0 X 0
When WE=1 and D=0
• The R-S Latch is “reset”
• The output is set to 0
• BUT, the data isn’t “stored” yet…not until WE goes to 0
• Then the R-S latch is in “hold” mode, and the latch has “latched onto” the data D
RESET 1 HOLD 1 HOLD 1 ILLEGAL 0
MCIT 593 – Introduction to Computer Systems Property of Penn Engineering 22

Gated D-Latch: Preventing “Illegal Action” of R-S Latch
Let’s add some logic to the R-S Latch…to prevent R-S’s illegal action
NAND Gate TT
R-S Latch Truth Table
D-Latch Truth Table
ACTION WE D Q
OPEN 1 1 1
OPEN 1 0 0 CLOSED 0 X 1 CLOSED 0 X 0
This is also the “open” action, why?
A B NAND ACTION S
011 RESET1
HOLD 1 ILLEGAL 0
Because “Q” is “following” D
The “D” in D-Latch stands for DATA; that we’d like to store in the latch
The “WE” on the D-Latch stands for “Write Enable”
When WE=1, the latch is “open” for DATA (it ‘follows’ the D input)
MCIT 593 – Introduction to Computer Systems Property of Penn Engineering 23

Gated D-Latch: Preventing “Illegal Action” of R-S Latch
Let’s add some logic to the R-S Latch…to prevent R-S’s illegal action
NAND Gate TT
R-S Latch Truth Table
D-Latch Truth Table
ACTION WE D Q
OPEN 1 1 1
OPEN 1 0 0 CLOSED 0 X 1 CLOSED 0 X 0
Once WE=0, the data is “stored”
A B NAND ACTION S 001SET0
011 101 110
RESET 1 HOLD 1 HOLD 1 ILLEGAL 0
Q is no longer “following” D
The last output is now stored in the latch
The RS latch is still in HOLD mode
The latch no longer “listens” to the D-input; it is “closed” so we mark D as “X”
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D-Latch Truth Table
• Truth Tables for Sequential Logic Gates are messy
• Outputs are no longer a function of only the inputs
• The last output is now a factor in determining output
• The notion of “Time dependence” is clear in our TTs
• We need a new type of truth table for sequential logic gates
• We introduce the “Timing Diagram” in the next section
D-Latch WE D Q ~Q OPEN 1001 OPEN 1110
CLOSED 0 X 0 1
CLOSED 0 X 1 0
We say latch is “open” or “closed”: Open if Q follows D, Closed if Q holds old value of Q
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BEYOND THE TRUTH TABLE:
THE TIMING DIAGRAM…AND ENTER THE COMPUTER’S CLOCK!
MCIT 593 – Introduction to Computer Systems Property of Penn Engineering

D-Latch Timing Diagram
• Diagram below is called a “Timing” Diagram
• Our D-Latch is previous-state dependent
• We can think of this as a time dependency
• Moving to the right on diagram, represents forward moving time
• The inputs & outputs to our D-Latch are on left
• Inputs/Outputs can be either “HIGH” (logic 1) or “LOW” (logic ) • Think of this as a time-dependent truth table
D-Latch WE D Q
OPEN 1 0 0
OPEN 1 1 1
CLOSED 0 X 0
CLOSED 0 X 1
Logic level =1
Logic level =0
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D-Latch Timing Diagram
• When the WE signal is high the latch is said to be open and the output signal, Q, follows the input signal, D (after a delay)
As in any combinational circuit there will be a small delay between the time that the input changes and the time that the output follows suit.
When latch is OPEN (WE=1): Notice, Q follows D
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D-Latch Timing Diagram
• When the WE signal is low the latch is closed and the output signal, Q retains (holds) its value.
When latch is CLOSED (WE=0): Notice, Q doesn’t follow D
closed open
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THE D-FLIP-FLOP
MCIT 593 – Introduction to Computer Systems Property of Penn Engineering

Flip-Flop (D-type) – Leader- Follower Configuration
By making the “WE” lines oppose:
• one latch will be OPEN while the other is CLOSED
• As WE is changed, the latches will flip/flop back and
forth between being opened and closed!
A new sequential “gate” known as a D-Flip-Flop 2 Inputs: D and CLK 2 Outputs: Q and Q’
MCIT 593 – Introduction to Computer Systems Property of Penn Engineering

Flip-Flop (D-type) – Leader- Follower Configuration
Q holds previous Q “follows” D 1 value of D
Let’s begin by getting the system to a known state
• We’ll put a 1 at the leader’s D-input
• We’ll set its WE to 1, opening the device
• A “1” will percolate through the leader latch (from D to Q)
• The second latch is CLOSED, but its output is unknown (X)
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Flip-Flop (D-type) – Leader- Follower Configuration
Q holds previous
value of D 1 Q “follows” D
Now we’ll change the CLK to 1
• This will cause the FOLLOWER to OPEN
• The data at its input will percolate through to its output (Q)
• The LEADER will be CLOSED…
• So even if the input changes to 0, it won’t matter
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Flip-Flop (D-type) – Leader- Follower Configuration
Q holds previous Q“follows”D 1 valueofD
When the “CLK” line goes back to 0
• The “follower” latch closes (holds onto the 1)
• The “leader” latch opens again, but…
…due to gate delays, the Q changes to 0…
…after the follower has closed!
Therefore…FOLLOWER’s output doesn’t change;
A 1 is still “stored” in this Flip-Flop
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Flip-Flop (D-type) – Leader- Follower Configuration
Q holds previous Q “follows” D value of D 0
When the “CLK” line goes back to 1
-The “follower” latch opens allowing the 0 to pass to its output -The “leader” latch is now closed
…even if the “leader’s” input changes (say to 1) The leader isn’t listening!
Now a 0 is stored in the Flip-Flop
MCIT 593 – Introduction to Computer Systems Property of Penn Engineering

Flip-Flop (D-type) – Leader- Follower Configuration
Q holds previous Q “follows” D value of D 0
What is the effect of the “flip-flop” behavior?
• The Flip-Flop only accepts new data when the CLK
transitions from 0 to 1
• This is referred to as an “edge triggered” device (instead of
level triggered)
• Why do it? Lengthens window of opportunity to read from
flipflop, and it shortens the window of opportunity to write
Called the “edge” of the CLK
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LATCHES VS. FLIP-FLOPS
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D-Latch – Level Triggered
Storage of information is triggered by WE’s logic level
• A D-Latch is a logic “level” triggered device
• Means the device is sensitive to the WE’s logic level
• In our case:
• When WE=1 (Write-enabled), Q follows D
• When WE=0 (Read-only), Q no longer follows D, holds onto last value of Q
D D-Latch Q WE
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D Flip-Flop – Edge Triggered
Positive edge of clock
• D Flip-Flop (DFF) is an “edge triggered” device
• Means, data is stored in device at the “edge” of the clock,
• In our case, this is a positive-edge-triggered device:
• Q follows D, only when CLK transitions from 0 to 1
• All other values of CLK, Q holds onto last value of D
• The D Flip-Flop takes a clock input (often denoted with triangle)
D DFF Q D DFF Q
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Level vs. Edge Triggering
For a D-Latch, windows of time to store/read information is equal
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When the WE is “HIGH” – D-latch is open, Q follows D
When the WE is “LOW” – D-latch is closed, data is stored & read-only
We prepare what we wish to store, right before latch closes
I open MCIT 593 – Introduction to Computer Systems

Level vs. Edge Triggering
• For a DFF, window of time for storage is shorter, but we have more time to read
• We can only store data into the DFF when the clock transitions from 0 to 1
• Otherwise the DFF is closed
• We prepare what we wish to store, right before the positive edge of the clock
Positive edge of clock
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What is the Clock?
A clock controls when stored values are “updated” • Oscillating global signal with fixed period
The clock will act as the ‘heartbeat’ of our system
• It creates “windows” of time to write or read to/from our storage devices
• Acts a like a “conductor” to synchronize information windows across our CPU
• The number of cycles per second is the clock frequency measured in cycles per second or Hertz (Hz)
• The clock period refers to the duration of one clock cycle. The period and frequency are inversely related.
• Example clock frequency: 2.5GHz = 2.5 x109 Hz
• So corresponding clock period = 1/(2.5 x 109) = .4×10-9 sec
• That would be: 0.4 nanoseconds
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LATCHES VS. FLIP-FLOPS VS. REGISTERS
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D-Latch to register
• A collection of D-latches, controlled by a common WE is called a register
• When WE=1, n-bit value D is written to the outputs
D3 D3Q MCIT 593 – Introduction to Computer Systems
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D Flip-Flop to register
• A collection of D Flip-Flops, controlled by a common CLK signal is also called a register
• When the CLK transitions from low to high, D is written to the outputs
D0 DFF Q0 D1 DFF Q1 D2 DFF Q2
D3 DFF3 Q CLK
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FINITE STATE MACHINES
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Let’s Build a Counter
• This system uses a DFF and an incrementer to “count” pulses of the clock! Clock
3 DFF3 +13 DQ
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Counter Timing Diagram
• Incrementer (+1) computes the next value of the DFF Clock
3 DFF3 +13 DQ
Realize: D and Q are 3-bit lines: so translate decimal #s to binary: ex: 3 indicates: 011
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012345 123456

Finite State Machine
• The counter we