程序代写 cuda GPU algorithm ppt/slideLayouts/slideLayout1.xml – cscodehelp代写
ppt/slideLayouts/slideLayout1.xml
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ppt/slideLayouts/slideLayout24.xml
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ppt/slideMasters/slideMaster1.xml
ppt/theme/theme1.xml
ppt/slideLayouts/slideLayout27.xml
ppt/slideLayouts/slideLayout28.xml
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ppt/slideLayouts/slideLayout30.xml
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ppt/slideLayouts/slideLayout50.xml
ppt/slideMasters/slideMaster2.xml
ppt/theme/theme2.xml
ppt/slides/slide1.xml
ppt/slides/slide2.xml
ppt/notesSlides/notesSlide1.xml
ppt/slides/slide3.xml
ppt/slides/slide4.xml
ppt/slides/slide5.xml
ppt/slides/slide6.xml
ppt/slides/slide7.xml
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ppt/slides/slide16.xml
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ppt/slides/slide20.xml
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ppt/slides/slide23.xml
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ppt/slides/slide25.xml
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ppt/slides/slide27.xml
ppt/slides/slide28.xml
ppt/slides/slide29.xml
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ppt/slides/slide32.xml
ppt/notesMasters/notesMaster1.xml
ppt/theme/theme3.xml
ppt/handoutMasters/handoutMaster1.xml
ppt/theme/theme4.xml
ppt/presProps.xml
ppt/viewProps.xml
ppt/tableStyles.xml
docProps/app.xml
docProps/core.xml
docProps/thumbnail.jpeg
docProps/custom.xml
ppt/media/image1.jpeg
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ppt/presentation.xml
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[Content_Types].xml
Add presentation title – Arial 32pt Add presenter name or subtitle – Arial 24pt
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Name, Department Body text – Arial 28pt Second text – Arial 28pt Third text – Arial 28pt Title and visual content – add slide title here Subtitle Body text – Arial 28pt Second text – Arial 28pt Third text – Arial 28pt Subtitle Please see slides at the end of this template for chart and table style guides. Copy and paste these items onto this page for ease.
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EEEE4115 Advanced Computational Engineering Introduction to GPU Programming with CUDA ®
The University of Nottingham Your Department Name etc
The GPU is seen as a ‘compute device’ to execute all or part of an application that: Can be isolated as a function Has to be executed many times Is highly data parallel Is lightweight The function when compiled to run on the ‘device’ is called a ‘Kernel’ NVIDIA’s CUDA: A Recap CUDA Programming Model
Allocate memory on device Allocated by cudaMalloc () Copy input arrays from host to device memory cudaMemcpy () Execute kernel(s) on the device kernel <<< block size, number of blocks, shared memory size >>>(parameters); Copy output arrays from device to host cudaMemcpy () NVIDIA’s CUDA: A Recap CUDA Programming Model
Each thread has a unique local index. Each block has a unique local index. These indices can be used to index data in arrays NVIDIA’s CUDA: A Recap Thread/Block Model
NVIDIA’s CUDA: A Recap Thread/Block Model int data [10] = { 2, 4, 6, 8, 10, 12, 14, 16, 18, 20} creates: 4 2 6 8 10 12 14 16 18 20 data 0 1 2 3 4 5 6 7 8 9 to select i th element: kernel <<<1,10>>>: int i = threadIdx.x ; do something with data[ i ]; kernel <<<10,1>>>: int i = blockIdx.x ; do something with data[ i ]; kernel <<<2,5>>>: int i = blockDim.x * blockIdx.x + threadIdx.x ; do something with data[ i ]; (kernel <<
NVIDIA’s CUDA: A Recap a[] = {1,2,3,4,5,6,7,8,9,…} (number of elements = int length ) 1 2 3 4 5 6 7 8 9 a: CPU code to access elements of a[] : void foo ( int *a, int *b) { for ( int i =0; i < length ;i ++){ b[ i ] = a[ i ]; } } NVIDIA’s CUDA: A Recap a[] = {1,2,3,4,5,6,7,8,9,…} (number of elements = int length ) GPU code to access elements of a[] using block of threads: __global__ void foo( int *a, int *b) { int index = threadIdx.x ; //unique thread ID if (index < length ) b[index] = a[index]; } Remember, max. number of threads = 512 or 1024 (hardware dependant) 1 2 3 4 5 6 7 8 9 a: thread no. 1 2 3 4 5 6 7 8 9 block no 1 1 2 3 4 5 6 7 8 9 a: a[] = {1,2,3,4,5,6,7,8,9,…} (number of elements = int length ) 1 2 3 4 5 6 7 8 9 a: GPU code to access elements of a[] using blocks of single threads: __global__ void foo( int *a, int *b) { int index = blockIdx.x ; //unique block ID if (index < length ) b[index] = a[index]; } Remember, max. number of blocks = 65535 1 2 3 4 5 6 7 8 9 a: block no. 1 2 3 4 5 6 7 8 9 thread no. 1 1 1 1 1 1 1 1 1 a[] = {1,2,3,4,5,6,7,8,9,…} (number of elements = int length ) 1 2 3 4 5 6 7 8 9 a: GPU code to access elements of a[] using blocks of n threads: e.g. n = 3: __global__ void foo( int *a, int *b) { int index = threadIdx.x+blockIdx.x * blockDim.x ; if (index < length ) b[index] = a[index]; } 1 2 3 4 5 6 7 8 9 block no 1 block no 2 block no 3 ….. a: thread no. 1 2 3 1 2 3 1 2 3 Example: Computing Illustrating memory types 3 tier reduction: Every thread adds a number of terms The first thread in each block adds all results from the block The CPU does the remaining reductions 3 types of memory Each thread uses private memory to store their partial results The first thread of a block needs access to all results in the block using shared memory The block totals need to by copied to CPU global memory Computing Approach Computing - Device Code allocate work to each thread each thread calculates their contribution to overall approximation wait for all threads to finish calculate sum of contributions from threads in each block Computing - Host Code CUDA error type assign total amount of work per thread/block allocate memory on device, copy arrays and check for errors call kernel copy sums from each block sum all Example: Computational Electromagnetics Porting the 1D TLM Algorithm to CUDA Transmission Line Method Founded and developed within the University for over 40 years Time domain method for the computation of electromagnetic fields Problems are discretised in time and space The computational domain being broken down into a mesh of transmission line segments connected at ‘nodes’ Extremely powerful and underpins the simulation strategies employed commercial software TLM Example: Aircraft Radome TLM Example: Aircraft Radome 1D TLM Algorithm The Algorithm - Consider a line in free space i.e. a wire. Problem space subdivided into N equal sections (nodes) . Simulation is then run for a total time T, over a number of time steps of ∆t.
